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peds82v16520a-01 1 semiconductor this version: nov. 2001 ms82v16520a preliminary 262,144-word 32-bit 2-bank sdram 1/36 general description the ms82v16520a is a 16-mbit system clock synchronous dynamic random access memory. features 262,144 words 32 bits 2 banks memory (1,024 rows 256 columns 32 bits 2 banks) single 3.3 v 0.3 v power supply lvttl compatible inputs and outputs programmable burst length (1, 2, 4, 8 and full page) programmable cas latency (2, 3) power down operation and clock suspend operation 2,048 refresh cycles/32 ms auto refresh and self refresh capability package: 100-pin plastic qfp (qfp100-p-1420-0.65-bk4) (product : ms82v16520a-xxga) xx indicates speed rank. product family family max. operating frequency access time package ms82v16520a-75 133 mhz 5.5 ns ms82v16520a-8 125 mhz 6 ns ms82v16520a-10 100 mhz 7 ns 100-pin plastic qfp
peds82v16520a-01 1 semiconductor ms82v16520a 2/36 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dq3 vccq dq4 dq5 vssq dq6 dq7 vccq dq16 dq17 vssq dq18 dq19 vccq vcc vss dq20 dq21 vssq dq22 dq23 vccq dqm0 dqm2 we cas ras cs ba(a10) a8 dq28 vccq dq27 dq26 vssq dq25 dq24 vccq dq15 dq14 vssq dq13 dq12 vccq vss vcc dq11 dq10 vssq dq9 dq8 vccq nc dqm3 dqm1 clk cke nc nc a9 dq2 vssq dq1 dq0 vcc nc nc nc nc nc nc nc nc nc nc vss dq31 dq30 vssq dq29 a0 a1 a2 a3 vcc nc nc nc nc nc nc nc nc nc nc vss a4 a5 a6 a7 100-pin plastic qfp pin name function pin name function a0 to a9 row address inputs we write enable a0 to a7 column address inputs dqm0 to dqm3 dq mask enable ba (a10) bank address dq0 to dq31 data inputs/outputs clk system clock input v cc supply voltage cke clock enable v ss ground cs chip select v cc q supply voltage for dq ras row address strobe v ss q ground for dq cas column address strobe nc no connection note: the same power supply voltage level must be provided to every v cc pin and v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin.
peds82v16520a-01 1 semiconductor ms82v16520a 3/36 block diagram timing register column decoders sense amplifiers dq0 to dq31 ra s ca s a0 to a9 ba bank controller internal col. address counter i/o controller column address buffers internal row address counter row address buffers 8 row decoders word drivers 8mb memory cells bank a read data register output buffers column decoders sense amplifiers input data register input buffers ck e cl k c s w e dqm0 to dqm3 ba 8 10 32 32 32 32 32 row decoders word drivers 8mb memory cells bank b 8
peds82v16520a-01 1 semiconductor ms82v16520a 4/36 pin description clk fetches all inputs at the "h" edge. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke, dqm0, dqm1, dqm2 and dqm3. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be masked so that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. address row & column multiplexed. row address: ra0 to ra9 column address: ca0 to ca7 ba selects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. ba = ?l?: bank a ba = ?h?: bank b ras cas we functionality depends on the combination. for details, see the function truth table. dqm0 to dqm3 masks the read data of two clocks later when dqm0 to dqm3 are set "h" at the "h" edge of the clock signal. masks the write data of the same clock when dqm0 to dqm3 are set "h" at the "h" edge of the clock signal. dqm0 controls dq0 to dq7, dqm1 controls dq8 to dq15, dqm2 controls dq16 to dq23, and dqm3 controls dq24 to dq31. dq0 to dq31 data inputs/outputs are multiplexed on the same pin. *notes: 1. when cs is set "high" at a clock transition from "low" to "high", all inputs except clk, cke, dqm0, dqm1, dqm2, and dqm3 are invalid. 2. when issuing an active, read or write command, the bank is selected by ba. ba active, read or write 0 bank a 1 bank b 3. when issuing a precharge command, the bank to be precharged is selected by the a9 and ba inputs. a9 ba operation 0 0 bank a is precharged. 0 1 bank b is precharged. 1 both banks are precharged.
peds82v16520a-01 1 semiconductor ms82v16520a 5/36 command operation mode register set command ( cs , ras , cas , we = ?low?) the ms82v16520a has the mode register that defines the operation mode ? cas latency, burst length, burst sequence?. the mode register set command should be executed just after the ms82v16520a is powered on. before entering this command, all banks must be precharged. next command can be issued after t rsc . auto refresh command ( cs , ras , cas = ?low?, we = ?high?) the auto refresh command performs refresh automatically by the address counter. the refresh operation must be performed 2,048 times within 32 ms and the next command can be issued after t rc from last auto refresh command. before entering this command, all banks must be precharged. self refresh entry/exit command ( cs , ras , cas , cke = ?low?, we = ?high?) the self refresh operation continues after the self refresh entry command is entered, with cke level left ?low?. this operation terminates by making cke level ?high?. the self refresh operation is performed automatically by the internal address counter on the ms82v16520a chip. in self refresh mode, no external refresh control is required. before entering self refresh mode, all banks must be precharged. next command can be issued after t rc . single bank precharge command ( cs , ras , we , a9 = ?low?, cas = ?high?) the single bank precharge command triggers bank precharge operation. precharge bank is selected by ba. all bank precharge command ( cs , ras , we = ?low?, cas , a9 = ?high?) the all bank precharge command triggers precharge of both bank a and bank b. if this command is executed during special bank active mode, the special bank active mode (automatic bank switching operation) is terminated. bank active command ( cs , ras = ?low?, cas , we = ?high?) the bank active command activates the bank selected by ba. the bank active command corresponds to conventional dram's ras falling operation. row addresses ?a0 to a9 and ba? are strobed. write command ( cs , cas , we , a9 = ?low?, ras = ?high?) the write command is required to begin burst write operation. then burst access initial bit column address is strobed. read command ( cs , cas , a9 = ?low?, ras , we = ?high?) the read command is required to begin burst read operation. then burst access initial bit column address is strobed. no operation command ( cs = ?low?, ras , cas , we = ?high?) the no operation command does not trigger any operation.
peds82v16520a-01 1 semiconductor ms82v16520a 6/36 device deselect command ( cs = ?high?) the device deselect command disables the ras , cas , we and address input. this command does not trigger any operation. data write/output enable command (dqmi = ?low?) the data write/output enable command enables dq0 to dq31 in read or write. the each dqm0, 1, 2 and 3 corresponds to dq0 to dq7, dq8 to dq15, dq16 to dq23 and dq24 to dq31 respectively. data mask/output disable command (dqmi = ?high?) the data mask/output disable command disables dq0 to dq31 in read or write. in read cycle output buffers are disabled after 2 clocks . in write cycle input buffers are disabled at the same clock. the each dqm0, 1, 2 and 3 corresponds to dq0 to dq7, dq8 to dq15, dq16 to dq23 and dq24 to dq31 respectively.
peds82v16520a-01 1 semiconductor ms82v16520a 7/36 truth table command truth table address function cs ras cas we ba a9 a8 to a0 device deselect h no operation l h h h mode register set l l l l op. code auto refresh l l l h bank activate l l h h ba ra read l h l h ba l ca (a7 to a0) write l h l l ba l ca (a7 to a0) precharge select bank l l h l ba l precharge all banks l l h l h burst stop l h h l dqm truth table function dqmi data write/output enable l data mask/output disable h
peds82v16520a-01 1 semiconductor ms82v16520a 8/36 function truth table (1/2) note 1 current state cs ras cas we ba address action note h nop lhhh nop lhhlba illegal 2 lhl ba ca illegal 2 l l h h ba ra row active l l l l l op-code mode register write l l h l ba a9 nop 4 idle lllh auto refresh/self refresh 5 h nop lhh nop lhlhba caread lhllba cawrite l l h h ba ra illegal 2 l l h l ba a9 precharge active (act) lll illegal h nop (continue row active after burst ends) lhhh nop (continue row active after burst ends) lhhl burst stop row active l h l h ba ca term burst, new read 3 l h l l ba ca term burst, start write 3 l l h h ba ra illegal 2 l l h l ba a9 term burst, execute precharge read (rd) lll illegal h nop (continue row active after burst ends) lhhh nop (continue row active after burst ends) lhhl burst stop row active l h l h ba ca term burst, start read 3 l h l l ba ca term burst, new write 3 l l h h ba ra illegal 2 l l h l ba a9 term burst, execute precharge 3 write (wt) lll illegal lll illegal h nop idle after t rp lhhh nop idle after t rp lhhlba illegal 2 lhl ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a9 nop 4 precharging (pre) lll illegal
peds82v16520a-01 1 semiconductor ms82v16520a 9/36 function truth table (2/2) note 1 current state cs ras cas we ba address action note h nop idle after t rc lhhh nop idle after t rc lhhlba illegal lhl ba ca illegal l l h h ba ra illegal l l h l ba a9 illegal refreshing (ref) lll illegal abbreviations ba = bank address ra = row address ca = column address nop = no operation command notes: 1. all inputs are enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. to avoid bus contention, satisfy t ccd and t dpl . 4. nop to bank precharging or in idle state. precharges activated bank by ba or a9. 5. illegal if any bank is not idle.
peds82v16520a-01 1 semiconductor ms82v16520a 10/36 function truth table for cke current state (n) cken-1 cken cs ras cas we address action note h invalid lhh exit self refresh abi lhlhhh exit self refresh abi lhlhhl illegal lhlhl illegal lhll illegal self refresh (sref) ll nop (maintain self refresh) h invalid lhh exit self refresh abi lhlhhh exit self refresh abi lhlhhl illegal lhlhl illegal lhll illegal power down (pd) ll nop (continue power down mode) hh refer to truth table 6 hlh enter power down 6 hllhhh enter power down 6 hllhhl illegal 6 hllhl illegal 6 hlllhl illegal 6 hllllh enter self refresh 6 h l llll illegal 6 all banks idle (abi) ll nop 6 hh refer to truth table hl begin clock suspend next cycle lh enable clock of next cycle any state other than listed above ll continue clock suspension note: 6. power-down and self refresh can be entered only when all the banks are in an idle state.
peds82v16520a-01 1 semiconductor ms82v16520a 11/36 mode set address keys operation code cas latency burst type burst length a8 a7 tm a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 0 0 mode setting 0 0 0 reserved 0 sequential 0 0 0 1 reserved 0 1 0 0 1 reserved 1 interleave 0 0 1 2 reserved 10 010 2 010 4 4 11 vender use only 011 3 011 8 8 write burst length 1 0 0 reserved 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 full page reserved power on sequence 1. with cke = "h", dqm = "h" and the other inputs in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply an auto-refresh 8 or more times. 5. enter the mode register command.
peds82v16520a-01 1 semiconductor ms82v16520a 12/36 burst length and sequence bl = 2 starting address (column address a0, binary) sequential type interleave type 0 0, 1 not supported 1 1, 0 not supported bl = 4 starting address (column address a1, a0, binary) sequential type interleave type 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 bl = 8 starting address (column address a2 to a0, binary) sequential type interleave type 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 bl = full: sequential only
peds82v16520a-01 1 semiconductor ms82v16520a 13/36 read/write command interval read to read command interval write to write command interval write to read command interval clk rd-a dq qb1 012345678 qb2 qb3 qa1 rd-b qb4 1cycle bl = 4, cl = 2 hi-z clk wt-a dq da1 012345678 db1 db2 db3 wt-b db4 1cycle bl = 4, cl = 2 hi-z clk wt-a dq da1 012345678 qb1 qb2 qb3 rd-b qb4 hi-z bl = 4 cl = 2 wt-a dq da1 qb1 qb2 qb3 rd-b qb4 hi-z 1cycle cl = 3
peds82v16520a-01 1 semiconductor ms82v16520a 14/36 read to write command interval clk dq 012345678 db1 db2 db3 rd-a wt-b dqm db4 hi-z 1cycle bl = 4, cl = 2, 3 cl = 2, 3 clk dq 012345678 qa2 qa3 rd-a wt-b dqm db1 db2 hi-z cl = 2 bl = 4, cl = 2, 3 dq qa1 qa2 rd-a wt-b dqm db1 db2 hi-z cl = 3 qa1 hi-z is necessary hi-z is necessary
peds82v16520a-01 1 semiconductor ms82v16520a 15/36 burst termination burst read termination by precharging in read cycle burst read termination by precharging in write cycle note: d5 data will not be written clk cl = 2 rd dq q1 012345678 pre cl = 3 rd dq pre q2 q3 q4 q1 q2 q3 q4 hi-z hi-z bl = 2, 4, 8, full act act t rp t rp clk cl = 2 wt dq d1 012345678 pre cl = 3 wt dq pre d2 d3 d4 d1 d2 d3 d4 hi-z hi-z bl = 2, 4, 8, full act act d5 t rp t rp d5
peds82v16520a-01 1 semiconductor ms82v16520a 16/36 read burst stop command write burst stop command clk cl = 2 rd dq q2 012345678 bst cl = 3 dq q3 q4 q2 q3 q4 hi-z hi-z bl = 2, 4, 8, full q1 q1 clk cl = 2, 3 wt dq d1 012345678 bst d2 d3 hi-z bl = 2, 4, 8, full d4
peds82v16520a-01 1 semiconductor ms82v16520a 17/36 electrical characteristics absolute maximum ratings parameter symbol rating unit voltage on power supply pin relative to gnd v cc ?0.5 to 4.6 v voltage on input pin relative to gnd v in , v out ?0.5 to v cc + 0.5 4.6 v short circuit output current i os 50 ma power dissipation p d *1 w operating temperature t opr 0 to 70 c storage temperature t stg ?55 to 150 c *: ta = 25 c recommended operating conditions (ta = 0 to 70c) parameter symbol min. typ. max. unit v cc 3.0 3.3 3.6 v power supply voltage v ss 000v input high voltage v ih 2.0 ? v cc + 0.3 v input low voltage v il ?0.3 ? 0.8 v capacitance (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) parameter symbol min. max. unit input capacitance (a0 to a9, ba) c in1 ?5pf input capacitance (clk, cke, cs , ras , cas , we dqm0 to dqm3) c in2 ?5pf output capacitance (dq0 to dq31) c out ?6pf
peds82v16520a-01 1 semiconductor ms82v16520a 18/36 dc characteristics test condition ms82v16520a-75 ms82v16520a-8 ms82v16520a-10 parameter symbol cke other min. max. min. max. min. max. unit note output high voltage v oh ?i oh = ?2.0 ma 2.4 ? 2.4 ? 2.4 ? v output low voltage v ol ?i ol = 2.0 ma ? 0.4 ? 0.4 ? 0.4 v input leakage current i li ? ? ?10 10 ?10 10 ?10 10 a output leakage current i lo ? ? ?10 10 ?10 10 ?10 10 a operating current (1 bank) i cc1 cke v ih t ck = min. t rc = min. no burst ? 200 ? 190 ? 180 ma 1, 2 i cc2p cke v il t ck = 15 ns ? 2 ? 2 ? 2 ma 3 precharge standby current in power down mode i cc2ps cke v il clk v il t ck = ?2?2?2ma2 i cc2n cke v ih cs v ih t ck = 15 ns ?40?40?40ma2 precharge standby current in non power down mode i cc2ns cke v ih clk v il t ck = ?20?20?20ma i cc3p cke v il t ck = 15 ns ? 3 ? 3 ? 3 ma 3 active standby current in power down mode i cc3ps cke v il clk v il t ck = ?3?3?3ma3 i cc3n cke v ih cs v ih t ck = 15 ns ?50?50?50ma3 active standby current in non power down mode i cc3ns cke v ih clk v il t ck = ?30?30?30ma3 operating current (burst mode) i cc4 cke v ih t ck = min. ? 240 ? 220 ? 200 ma 2 refresh current i cc5 cke v ih t rc min. ? 160 ? 150 ? 140 ma self refresh current i cc6 cke 0.2v ??3?3?3ma notes 1. the maximum value of power supply current is obtained with the output open. 2. address and data are changed only one time during one cycle. 3. address and data are changed only one time during two cycles.
peds82v16520a-01 1 semiconductor ms82v16520a 19/36 ac characteristics test conditions ac measurements assume t t = 1 ns. reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih (min.) and v il (max) . an access time is measured at 1.4 v. input levels at the ac testing are 2.4 v/0.4 v. t ck t ch t cl t setu p t hold t oh clk input output 2.4 v 1.4 v 0.4 v 2.4 v 1.4 v 0.4 v 1.4 v 1.4 v t ac
peds82v16520a-01 1 semiconductor ms82v16520a 20/36 synchronous characteristics ms82v16520a-75 ms82v16520a-8 ms82v16520a-10 parameter symbol min. max. min. max. min. max. unit note cas latency = 3 t ck3 7.5 ? 8 ? 10 ? ns clock cycle time cas latency = 2 t ck2 12 ? 12 ? 15 ? ns cas latency = 3 t ac3 ?5.5?6?7ns1 access time from clk cas latency = 2 t ac2 ?8?8?9ns1 clk high level width t ch 3 ? 3 ? 3.5 ? ns clk low level width t cl 3 ? 3 ? 3.5 ? ns data-out hold time t oh 3?3?3?ns data-out low-impedance time t lz 0?0?0?ns data-out high-impedance time t hz ?5.5?6?7ns data-in setup time t ds 2 ? 2.5 ? 2.5 ? ns data-in hold time t dh 1?1?1?ns address setup time t as 2 ? 2.5 ? 2.5 ? ns address hold time t ah 1?1?1?ns cke setup time t cks 2 ? 2.5 ? 2.5 ? ns cke hold time t ckh 1?1?1?ns command ( cs , ras , cas , we , dqm) setup time t cms 2 ? 2.5 ? 2.5 ? ns command ( cs , ras , cas , we , dqm) hold time t cmh 1?1?1?ns note 1. output load. z = 50 ? 1.4 v output 30 pf 50 ?
peds82v16520a-01 1 semiconductor ms82v16520a 21/36 asynchronous characteristics ms82v16520a-75 ms82v16520a-8 ms82v16520a-10 parameter symbol min. max. min. max. min. max. unit note ref to ref/act command period t rc 67.5 ? 72 ? 90 ? ns act to pre command period t ras 45 120k 48 120k 60 120k ns pre to act command period t rp 22.5 ? 24 ? 30 ? ns delay time act to read/write command t rcd 22.5 ? 24 ? 30 ? ns act (0) to act (1) command period t rrd 15 ? 16 ? 20 ? ns read/write to read/write command period t ccd 7.5 ? 8 ? 10 ? ns data-in to pre command period t dpl 7.5 ? 8 ? 10 ? ns data output to write command input time t owd 15 ? 16 ? 20 ? ns mode register set cycle time t rsc 15 ? 16 ? 20 ? ns transition time t t 130130130ns refresh time t ref ?32?32?32ms
peds82v16520a-01 1 semiconductor ms82v16520a 22/36 timing waveform read/write cycle (bl = 2, cl = 3) clk 012 3 456 78 9101112131415 16 17 18 19 cke cs cas we ba t ck t ch t cl t cms t cmh t cks t as t ah t ckh ras add a9/ ap dqm 0 - 3 dq raa t cms t cmh t ac t oh t hz t lz t ds t dh caa raa cab dab1 dab2 rba rba qaa1 qaa2 hi-z t rcd t ras t rc t dpl t rp act-a rd-a wt-a pre-a act-b t owd
peds82v16520a-01 1 semiconductor ms82v16520a 23/36 mode register set hi-z pre-all h mra act t rsc t rp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 24/36 auto refresh hi-z t rc pre-all l h ref ref act t rc t rp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 25/36 self refresh (entry and exit) hi-z t rc pre-all l h self entry act t rc t rp self exit self entry self exit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 26/36 burst termination by precharging (bl = 8, cl = 3) h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba hi-z act-a l wt-a pre command termination raa caa raa rab rab pre-a daa1 daa2 qab1 qab2 qab3 qab4 cab rd-a act-a pre-a pre command termination add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 27/36 power down mode and clock suspension (bl = 4, cl = 2) hi-z act-a l pd entry pd exit clock mask start pre-a raa raa caa active standby rd-a qaa2 qaa3 qaa4 clock mask end pd entry pd exit precharge standby qaa1 add a9/ ap dqm 0 - 3 dq t cks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba ras
peds82v16520a-01 1 semiconductor ms82v16520a 28/36 clock suspend exit & power down exit 1) clock suspend (= active power down) exit 2) power down (= precharge power down) exit notes: 1. active power down: one or both bank active state. 2. precharge power down: both bank precharge state. 3. nop should be issued. and new command can be issued after 1 clock. clk internal clk command cke rd t cks note 1 clk cke internal clk command act t cks note 3 nop note 2
peds82v16520a-01 1 semiconductor ms82v16520a 29/36 byte read/write operation (by dqm) (bl = 4, cl = 3) h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba ras dqm1 dqm0 rba cba cbb add rba a9/ ap dq 0 - 7 dq 8 - 15 qba1 qba3 qba3 qba2 qba2 qba4 dbb3 dbb1 dbb2 dbb2 dbb4 act-b rd-b byte of dq8-15 not read wt-b dq8-15 byte of not write byte of dq0-7 not write byte of dq0-7 not write byte of dq0-7 not read
peds82v16520a-01 1 semiconductor ms82v16520a 30/36 burst read and single write (bl = 4, cl = 3) h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba hi-z act-b l rd-b raa caa raa single wt qaa1 qaa2 qaa3 qaa4 dbb dbc cbb single wt pre-b cbb add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 31/36 random column read (continuous read of same bank) (bl = 4, cl = 3) h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba act-a raa raa caa qaa1 qaa3 rd-a qaa2 qab1 qaa4 cab qab2 qac2 qac1 rai rai pre-a act-a l rd-a rd-a cac qac4 qac3 add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 32/36 random column write (continuous write of same bank) (bl = 4, cl = 3) h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba act-b rba rba cba dba1 dba3 wt-b dba2 dbb1 dba4 cbb cbc dbb2 dbc2 dbc1 rbi rbi pre-b act-b l dbc4 dbc3 wt-b wt-b add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 33/36 interleaved column read (bl = 4, cl = 3) h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba act-a raa raa caa cba cbb qaa1 qaa3 rd-a qaa2 qba1 qaa4 cab qba2 qbc2 qbb1 pre-b pre-a rba rba qab2 qab1 act-b rd-b t rcd t rrd l qab4 qab3 rd-a rd-b add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 34/36 interleaved column write (bl = 4, cl = 3) h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba act-a raa raa daa1 daa3 wt-a daa2 dba1 daa4 dba2 dbb2 dbb1 pre-b pre-a dab2 dab1 act-b wt-b wt-a t rcd t rrd l caa cba cbb cab rba rba wt-b dab4 dab3 add a9/ ap dqm 0 - 3 dq ras
peds82v16520a-01 1 semiconductor ms82v16520a 35/36 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp100-p-1420-0.65-bk4 mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.54 typ. 5 rev. no./last revised 4/nov. 28, 1996 (unit: mm)
peds82v16520a-01 1 semiconductor ms82v16520a 36/36 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2001 oki electric industry co., ltd.

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